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2011 Microchip Technology Inc.

DS39932D-page 187

PIC18F46J11 FAMILY

11.3.5

CHIP SELECT FEATURES

One chip select line, PMCS, is available for the Master

modes of the PMP. The chip select line is multiplexed

with the second Most Significant bit (MSb) of the

address bus (PMADDRH<6>). When configured for

chip select, the PMADDRH<7:6> bits are not included

in any address auto-increment/decrement. The

function of the chip select signal is configured using the

chip select function bits (PMCONL<7:6>).

11.3.6

AUTO-INCREMENT/DECREMENT

While the module is operating in one of the Master

modes, the INCMx bits (PMMODEH<4:3>) control the

behavior of the address value. The address can be

made to automatically increment or decrement after

each read and write operation. The address increments

once each operation is completed and the BUSY bit

goes to ‘0’. If the chip select signals are disabled and

configured as address bits, the bits will participate in

the increment and decrement operations; otherwise,

the CS1 bit values will be unaffected.

11.3.7

WAIT STATES

In Master mode, the user has control over the duration

of the read, write and address cycles by configuring the

module Wait states. Three portions of the cycle, the

beginning, middle and end, are configured using the

corresponding WAITBx, WAITMx and WAITEx bits in

the PMMODEL register.

The WAITBx bits (PMMODEL<7:6>) set the number of

Wait cycles for the data setup prior to the

PMRD/PMWT strobe in Mode 10, or prior to the

PMENB strobe in Mode 11. The WAITMx bits

(PMMODEL<5:2>) set the number of Wait cycles for

the PMRD/PMWT strobe in Mode 10, or for the PMENB

strobe in Mode 11. When this Wait state setting is ‘0’,

then WAITB and WAITE have no effect. The WAITE

bits (PMMODEL<1:0>) define the number of Wait

cycles for the data hold time after the PMRD/PMWT

strobe in Mode 10, or after the PMENB strobe in

Mode 11.

11.3.8

READ OPERATION

To perform a read on the PMP, the user reads the

PMDIN1L register. This causes the PMP to output the

desired values on the chip select lines and the address

bus. Then the read line (PMRD) is strobed. The read

data is placed into the PMDIN1L register.

If the 16-bit mode is enabled (MODE16 = 1), the read

of the low byte of the PMDIN1L register will initiate two

bus reads. The first read data byte is placed into the

PMDIN1L register, and the second read data is placed

into the PMDIN1H.

Note that the read data obtained from the PMDIN1L

read operation. Hence, the first user read will be a

dummy read to initiate the first bus read and fill the read

ready until after the BUSY bit is observed low. Thus, in

a back-to-back read operation, the data read from the

of the register will yield the new value.

11.3.9

WRITE OPERATION

To perform a write onto the parallel bus, the user writes

to the PMDIN1L register. This causes the module to

first output the desired values on the chip select lines

and the address bus. The write data from the PMDIN1L

the write line (PMWR) is strobed. If the 16-bit mode is

enabled (MODE16 = 1), the write to the PMDIN1L

consist of the data contained in PMDIN1L and the

second write will contain the PMDIN1H.

11.3.10

PARALLEL MASTER PORT STATUS

11.3.10.1

The BUSY Bit

In addition to the PMP interrupt, a BUSY bit is provided

to indicate the status of the module. This bit is used

only in Master mode. While any read or write operation

is in progress, the BUSY bit is set for all but the very last

CPU cycle of the operation. In effect, if a single-cycle

read or write operation is requested, the BUSY bit will

never be active. This allows back-to-back transfers.

While the bit is set, any request by the user to initiate a

new operation will be ignored (i.e., writing or reading

the lower byte of the PMDIN1L register will neither

initiate a read nor a write).

11.3.10.2

Interrupts

When the PMP module interrupt is enabled for Master

mode, the module will interrupt on every completed

read or write cycle; otherwise, the BUSY bit is available

to query the status of the module.

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